Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple processor dice, multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, or logical processors.
The ever increasing number of processing elements—cores, hardware threads, and logical processors—on integrated circuits enables more tasks to be accomplished in parallel. However, as a corollary to the increased processing power, the problems with thermal density and leakage power are also amplified. As a result, processors with multiple cores may employ a heat dissipation technique called core hopping—moving of at least one core's architecture state/context to another core. However, inherent with moving entire context from one core to another is the cost—wasted execution cycles, energy spent on the move, and cold caches. Yet, currently there is no intelligent decision on when to core hop outside of the initial core hop decision based on thermal density. As a result, a core hop may be initiated when a core hop is not needed—a triggering, thermal-density condition may be self-alleviating—or may be infeasible—the hop results in the same or worse thermal conditions. As a consequence, there are some circumstances where a core hop is triggered due to thermal conditions, but it's advantageous to avoid the core hop.
As the heat and power concerns for processors continue to escalate, the intelligent use of low power states becomes more important. Currently, today's privileged level software—Operating Systems—are not extremely accurate in requesting transition to low power states. As a result, previous software may request a core to enter a specific low power state that is inefficient either from being too deep—lower power consumed but not sufficient wake time in comparison to the amount of time the core is going to be idle in the future—or to shallow—more power consumed when the amount of idle time is greater than the wake time.